This invention relates generally to semiconductor memory devices, and more particularly the invention relates to a high speed electrically programmable read-only memory (EPROM) cell and array.
The EPROM array typically employs a single floating gate transistor memory cell. In present technologies an EPROM cell measures approximately 6 microns by 6 microns with the transistor width and length being approximately 1.5 micron and 2 microns, respectively. This small cell size allows the fabrication of large memory arrays (e.g. 512K memories), and requires a small programming current. A major disadvantage, however, is the low cell current and consequent slow speed (e.g. 200-450 nanoseconds). Additionally, high voltage thresholds are required for device operation. Thus the conventional EPROM cell is suitable for high density applications but cannot complete with high speed bipolar memories. While merely making the conventional cell larger would increase read current and speed, the required programming current would be unacceptably large, and the threshold voltage of the unprogrammed transistor would remain unchanged.